1. Field of the Invention
The embodiments discussed herein relate to a semiconductor device and a method of manufacturing a semiconductor device.
2. Description of the Related Art
Improvement of the characteristics of power semiconductor devices with a breakdown voltage class of 600 V, 1200 V, and 1700 V such as insulated gate bipolar transistors (IGBTs), free wheeling diodes (FWDs), and the like is advancing. These power semiconductor devices are used in power converting equipment such as highly efficient and power-saving inverters and the like, and are indispensable for controlling motors. There is urgent market demand for power semiconductor devices for such applications to have lower loss (more power-saving), higher speed, higher efficiency, and less adverse impact on the environment.
In response to such demands, with respect to the IGBTs, a method of fabricating a low-cost semiconductor device whose electric loss is low such as a low on-voltage has been proposed. For example, to prevent breakage of the wafer during the wafer processing, the wafer processing is started using a thick semiconductor wafer, which is ordinarily employed. At a process step as late in the wafer processing as possible, the semiconductor wafer is ground from a back surface thereof on the side opposite that of a front surface on which a MOS gate (an insulated gate including a metal oxide semiconductor) structure is formed, whereby the thickness of the semiconductor wafer reduced as much as possible to the extent that desired properties are acquired. An impurity is ion-implanted at a desired impurity concentration from the back surface after the grinding of the wafer and is activated, and a collector layer is thereby formed on the back surface side of the wafer.
The development and the manufacture of semiconductor devices that use the method of realizing a low-loss property at a low cost by reducing the thickness of the semiconductor wafer as described above have recently become mainstream especially for power semiconductor devices. For IGBTs in particular, to further facilitate reduction of the loss, an indispensable process step involves forming a field stop (FS) layer at a position deeper than a collector layer from the back surface of the wafer on the collector side of the drift layer by ion-implanting an impurity from the back surface after the grinding of the semiconductor wafer. The field stop layer is a semiconductor layer whose impurity concentration is higher than that of the drift layer and whose conductivity type is same as that of the drift layer, and has a function of suppressing a depletion layer that extends from a pn-junction between a base region and the drift layer such that the depletion layer does not reach the collector layer during turn off.
To facilitate overall size reductions of a power converting device (a related chip including an IGBT), development is also advancing for a reverse conducting-IGBT (RC-IGBT) that has a structure formed by integrating an IGBT and an FWD connected in reverse-parallel to the IGBT with each other, by incorporating the IGBT and the FWD in one same semiconductor chip. A configuration of a conventional RC-IGBT will be described taking an example of a configuration formed by integrating an IGBT including a field stop layer (an FS-IGBT) and an FWD connected in reverse-parallel to the FS-IGBT with each other, by incorporating the FS-IGBT and the FWD in one same semiconductor chip. FIG. 17 is a cross-sectional view of the configuration of the conventional RC-IGBT having the field stop structure.
As depicted in FIG. 17, in the conventional RC-IGBT, a trench-gate MOS gate (an insulated gate including a metal oxide semiconductor) structure 120 is formed on the side of the front surface of an n−-type semiconductor substrate to be an n−-type drift layer 101 in an IGBT portion 121. The MOS gate structure 120 includes a p-type base region 102, a trench 103, a gate oxide film 104, a gate electrode 105, an n+-type emitter region 106, and a p+-type contact region 107. An emitter electrode 108 contacts the n+-type emitter region 106 and the p+-type contact region 107. The emitter electrode 108 generally includes Al (aluminum)-Si (silicon).
The p-type base region 102, the trench 103, the emitter electrode 108, and an interlayer insulating film 109 are formed from the IGBT portion 121 to the FWD portion 122. In the FWD portion 122, the p-type base region 102 and the emitter electrode 108 also respectively act as a p-type anode region and an anode electrode of the FWD. A favorable ohmic contact (electrical contact presenting an ohmic property (linearity)) with the p-type base region 102 may be realized in the IGBT portion 121 by using Ai-Si as the electrode material of the emitter electrode 108 as described above. Favorable ohmic contact with the p-type base region 102 (the p-type anode region) may be realized also in the FWD portion 122 by using Ai-Si as the electrode material of the emitter electrode 108.
An n-type field stop layer 110, a p+-type collector region 111, and an n+-type cathode region 112 are formed on the back surface side of the n− semiconductor substrate. The p+-type collector region 111 is formed in the IGBT portion 121. The n+-type cathode region 112 is formed in the FWD portion 122 side by side with (parallel to) the p+-type collector region 111. The p+-type collector region 111 and the n+-type cathode region 112 are formed at positions shallower than the n-type field stop layer 110 from the back surface of the n−-type semiconductor substrate. The collector electrode 113 also acts as the cathode electrode and contacts the p+-type collector region 111 and the n+-type cathode region 112.
A device has been proposed as the above RC-IGBT where, in addition to a first trench having a gate electrode embedded therein through the gate insulating film, a second trench reaching the inside of the p-type base region is formed and an emitter electrode is embedded in the second trench (see, e.g., Japanese Laid-Open Patent Publication No. 2009-027152 (Paragraph 0054, FIG. 1)). In Japanese Laid-Open Patent Publication No. 2009-027152, a barrier metal is formed along the inner wall of the second trench using titanium (Ti), tungsten (W), or the like. In Japanese Laid-Open Patent Publication No. 2009-027152, the emitter electrode is electrically connected to an n+-type emitter region and a p+-type contact region in an IGBT portion and the p-type base region (a p-type anode region) in the FWD portion, through the barrier metal.
A device has been proposed as another RC-IGBT where, the width of each contact hole in the FWD portion and an FWD operating portion in the IGBT portion is larger than the width of each contact hole in the IGBT operation unit (see, e.g., Japanese Laid-Open Patent Publication No. 2013-021304). In Japanese Laid-Open Patent Publication No. 2013-021304, the recovery property is improved by reducing the area density of the p-type impurity in the FWD operating portion in the IGBT portion and thereby suppressing injection of holes into the FWD portion. A device has been proposed as a conventional diode whose anode electrode is formed using an alloy formed by including silicon at 1% in aluminum (AlSi1%) (see, e.g., Japanese Laid-Open Patent Publication No. 2007-059801 (Paragraph 0036)).